The present invention is related to data processing systems using shared resources, and more particularly to an improved semaphore for controlling the access of a shared memory resource by two or more microcomputers.
The use of shared memory resources for transferring information between two or more microcomputers has become increasingly important due to the wide spread use of distributed processing techniques where control tasks are distributed among a number of microcomputers. A prior art semaphore described in the instant assignee's patent application, Ser. No. 187,259 (U.S. Pat. No. 4,380,798), entitled "Semaphore Register Including Ownership Bits", invented by Paul D. Shannon et al, filed on Sept. 15, 1980, and used in the Motorola Type MC68120/MC68121 Intelligent Peripheral Controller (hereinafter called "IPC"), provides a means of arbitrating so called simultaneous accesses of a shared memory by the IPC microprocessor and a second microprocessor. However, the IPC microprocessor and the second microprocessor must be either operating synchronously or, if operating asynchronously, must be synchronized to one another by means of an additional IPC control signal. Moreover, most commercially available microprocessors, microcomputers and computers are not compatible with the IPC control signals required for asynchronous operation, and therefore, must be operated in synchronism with the IPC microprocessor in order to use the IPC semaphore. But, in many applications, it is desirable to operate multiple processors asynchronously at the same speed or even at different speeds, and at the same time, utilize semaphores for governing simultaneous access of shared memories. However, since prior art semaphores cannot accomodate such asynchronously operating microcomputers or even multiple microprocessors, there is a need for an improved semaphore which can arbitrate the simultaneous access of memory resources shared by two or more asynchronous microcomputers.